1. Field of the Invention
Embodiments of the invention relate to a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Related Art
Silicon carbide (SiC) is anticipated to be a next generation semiconductor material of silicon (Si). Compared to conventional semiconductor devices using Si as a material, semiconductor devices using silicon carbide (hereinafter, silicon carbide semiconductor device) have various advantages such as reducing device resistivity in the ON state to several hundredths and use in environments of high temperatures (200 degrees C. or more). Such advantages are enabled by characteristics of the material itself such as the bandgap of SiC being about 3 times that of Si and the dielectric breakdown field strength being nearly 10 times that of Si.
Schottky barrier diodes (SBD) and planar vertical metal oxide semiconductor field effect transistors (MOSFET) have become commercial SiC semiconductor devices.
A trench gate structure is a 3-dimensional structure in which a metal oxide semiconductor (MOS) gate (MOS insulated gate) is embedded in a trench formed in a semiconductor base formed of silicon carbide (hereinafter, silicon carbide base) and a portion along a trench side wall is used as a channel (inversion layer). Therefore, when the device area (chip area) is compared between devices of the same on-resistance (Ron), the device area of the trench gate structure can be made significantly smaller than that of a planar gate structure in which a MOS gate is provided in a flat shape on a silicon carbide base and thus, a trench gate structure may be considered a promising device structure.
A structure of a conventional silicon carbide semiconductor device will be described taking a vertical MOSFET of a trench gate structure as an example. FIG. 24 is a cross-sectional view of a structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device depicted in FIG. 24 includes a MOS gate of a typical trench gate structure on a front surface (surface on a p-type base region 104 side) side of a semiconductor base formed of silicon carbide (hereinafter, silicon carbide base) 100. The silicon carbide base (semiconductor chip) 100 is formed by sequentially forming by epitaxial growth on an n+-type supporting substrate formed of silicon carbide (hereinafter, n+-type silicon carbide substrate) 101, an n−-type drift region 102, an n-type current spreading region 103, and the p-type base region 104 forming silicon carbide layers.
In the n-type current spreading region 103, a first p-type region 111 is selectively provided to cover a bottom of a trench 107 entirely. The first p-type region 111 is provided to a depth reaching the n−-type drift region 102. Further, a second p-type region 112 is selectively provided between adjacent trenches 107 (mesa portion), in the n-type current spreading region 103. The second p-type region 112 contacts the p-type base region 104 and is provided to a depth reaching the n−-type drift region 102. Reference numerals 105, 106, 108, 109, and 113 to 115 are an n+-type source region, a p++-type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode, respectively.
As such a vertical MOSFET of a trench gate structure, a device has been proposed that includes a p-type base layer of a 2-layer structure having p-type semiconductor layers of differing impurity concentrations, sequentially formed by epitaxial growth (for example, refer to Japanese Patent Application Laid-Open Publication No. 2012-099601 (paragraph 0030, FIG. 1) and Japanese Patent Application Laid-Open Publication No. 2015-072999 (paragraph 0060, FIG. 9)). In Japanese Patent Application Laid-Open Publication Nos. 2012-099601 and 2015-072999, among the p-type semiconductor layers forming the p-type base layer, punch-through is suppressed at the p-type semiconductor layer of the higher impurity concentration and the on-resistance is reduced at the p-type semiconductor layer of the lower impurity concentration.
As a method of manufacturing such a vertical MOSFET of a trench structure, a method of ion implanting a p-type impurity to form a p-type base region forming a channel has been proposed (for example, refer to Japanese Patent Application Laid-Open Publication No. 2014-241435 (paragraphs 0020, 0021, 0028, FIGS. 2, 3)). In Japanese Patent Application Laid-Open Publication No. 2014-241435, the p-type base region has an impurity concentration distribution in which the impurity concentration increases as the depth from the substrate front surface increases, the maximum impurity concentration occurs at a predetermined depth, and the impurity concentration decreases as the depth from the substrate front surface increases; and the p-type base region is formed within a depth range where short channel effect occurs.